• 1.Introduction
• 2.Design on MDLE
• 2.1 Moore Graph State
• 2.2 First method - with 2 T flip-flops
• 2.3 Simulation on MDLE with 2 T flip-flops
• 2.4 Second Method - with 2 JK flip-flops
• 2.5 Simulation on MDLE with 2 JK flip-flops
• 3.Implementation on Xilinx Spartan-6 FPGA board - Nexys 3
• 3.1 Design creation with Xilinx ISE software
• 3.2 GUI with real time interaction on FPGA board

1.Introduction :

We want to implement on a Nexys 3 board a robot toy module which simulates sleeping. Its interface is :

The toy should work as follows :

• the state of the toy is reassessed every 2 seconds to the clock rate of H.
• when the toy is awake, his eyes are opened and he laughs.
• when the toy is in a state of light sleep, his eyes are closed and he growls.
• when the toy is in a state of deep sleep, his eyes are closed and he snores.
• when the toy is in distress, he cries and his eyes are opened.
• the toy into waking state remains on waking state with the light on , even if there is noise.
• for puting the toy in a state of light sleep, it is from the waking state, then turn off the light and in the absence of noise. Turning off the light with noise places the toy in distress.
• when the toy is in distress state, he returned to the waking state to the next clock edge where the light is on, with some noise or not. Otherwise it remains in distress.
• when the toy is in a state of light sleep, it goes into deep sleep if the light continues to be extinguished without noise. Any other manipulation brings the toy in distress state.
• the toy remains in a state of deep sleep if the light is off and there is no noise.
• when the toy is in a state of deep sleep and the light comes on in the absence of noise, the toy goes to the waking state. Any other manipulation brings the toy in distress.

2.Design on MDLE :

We first design the state graph of the toy which will be Moore type. After having got the corresponding module, we will implement it in SHDL (Simple Hardware Description Language) as the MDLE tool developed by Jean-Christophe Buisson in the IT department of ENSEEIHT.

• 2.1 Moore Graph State :

  The inputs are noted in the order light - noise (L - B) and the outputs eyes - voice (s[2] - s[1] - s[0]). According to the specifications above, the toy robot has four possible states :

  
  
  • awake (opened eyes and he laughts) ; output = 101 ; denoted AW
  • light sleeping (closed eyes and he growls) ; output = 010; denoted LS
  • deep sleeping (closed eyes and he snores) ; output = 000 ; denoted DS
  • distress (opened eyes and he cries) ; output = 111 ; denoted DI
  
  
  We deduce the following Moore State graph :
  
  
  

  

  
  

  Here is the transition table that results :

  
  

  inputs	state before	state after
  00	101	010
  01	101	111
  10	101	101
  11	101	101
  00	111	111
  01	111	111
  10	111	101
  11	111	101
  00	010	000
  01	010	111
  10	010	111
  11	010	111
  00	000	000
  01	000	111
  10	000	101
  11	000	111

  
  

  We calculate in two ways the relationship between outputs and inputs, the first method with 2 T flip-flops and the second with 2 JK flip-flops. With the heuristic rules whose goal is to minimize the number of bits that change (states or outputs) in the states changing, we make the following assignment :

  
  
  
• 2.2 First method - with 2 T flip-flops :
  
  
  

  Tx	Ty	LB	XY time instant n	XY time instant n+1
  1	0	00	00	10
  0	1	01	00	01
  0	0	10	00	00
  0	0	11	00	00
  0	0	00	01	01
  0	0	01	01	01
  0	1	10	01	00
  0	1	11	01	00
  0	1	00	10	11
  1	1	01	10	01
  1	1	10	10	01
  1	1	11	10	01
  0	0	00	11	11
  1	0	01	11	01
  1	1	10	11	00
  1	0	11	11	01

  
  
  

  Thanks to the Karnaugh tables, we calculate relations on Tx and Ty :

  
  

  Table $\,{\large \text{T$_{x}$}}$	Table $\,{\large \text{T$_{y}$}}$

  
  

  so we get :

  \begin{equation} {\large \text{T$_{x}$}=\overline{\text{L}}\,\overline{\text{B}}\,\overline{\text{X}}\,\overline{\text{Y}}+\text{X}\,\text{B}+\text{X}\,\text{L}\quad\quad\quad\quad\quad \text{T$_{y}$}=\text{X}\,\overline{\text{Y}}+\overline{\text{L}}\,\text{B}\,\overline{\text{Y}}+ \text{L}\,\overline{\text{X}}\,\text{Y}+\text{L}\,\overline{\text{B}}\,\text{Y}} \end{equation}
  

  Express now from the following table the outputs in terms of X and Y :

  
  

  XY	Outputs (s[2] s[1] s[0])
  00	101
  10	010
  01	111
  11	000

  
  

  It comes :

  \begin{align} S[2]\,&{\large =\overline{\text{X}}\,\overline{\text{Y}}+\overline{\text{X}}\,\text{Y}=\overline{\text{X}}\,(\overline{\text{Y}}+\text{Y})=\overline{\text{X}}}\\ S[1]\,&{\large =\text{X}\,\overline{\text{Y}}+\overline{\text{X}}\,\text{Y}=\text{X}\,\oplus\,\text{Y}}\\ S[0]\,&{\large =\overline{\text{X}}\,\overline{\text{Y}}+\overline{\text{X}}\,\text{Y}=\overline{\text{X}}\,(\overline{\text{Y}}+\text{Y})=\overline{\text{X}}} \end{align}
  
• 2.3 Simulation on MDLE with 2 T flip-flops :

  The MDLE tool allows to simulate the operation of combinational and sequential circuits. It uses the language SHDL (Simple Hardware Description Language). In order to be teaching, his writing is very simple and enables the design of modules in a more condensed form that others standard hardware description languages ​​like VHDL. For more information about the syntax, see here.

  Here is the source robot_first.mdl corresponding to the module designed with 2 T flip-flops :

  
  
  

  We can load the design with the graphical editor, like this :

  
  
  

  With the MDLE simulator, we can browse the Moore graph as a function of time and inputs. This is illustrated on the following video :

  
  
  
  
• 2.4 Second Method - with 2 JK flip-flops :
  
  
  

  Jx	Kx	Jy	Ky	LB	XY time instant n	XY time instant n+1
  1	0	0	0	00	00	10
  0	0	1	0	01	00	01
  0	0	0	0	10	00	00
  0	0	0	0	11	00	00
  0	0	0	0	00	01	01
  0	0	0	0	01	01	01
  0	0	0	1	10	01	00
  0	0	0	1	11	01	00
  0	0	1	0	00	10	11
  0	1	1	0	01	10	01
  0	1	1	0	10	10	01
  0	1	1	0	11	10	01
  0	0	0	0	00	11	11
  0	1	0	0	01	11	01
  0	1	0	1	10	11	00
  0	1	0	0	11	11	01

  
  
  

  We calculate with the Karnaugh tables the relations of Jx, Kx, Ky and Jy :

  
  

  Table $\,{\large \text{J$_{x}$}}$	Table $\,{\large \text{K$_{x}$}}$

  
  

  which gives :

  \begin{equation} {\large \text{J$_{x}$}=\overline{\text{L}}\,\overline{\text{B}}\,\overline{\text{X}}\,\overline{\text{Y}}\quad\quad\quad\quad\quad \text{K$_{x}$}=\text{B}\,\text{X}+\text{L}\,\text{X}} \end{equation}
  
  

  Table $\,{\large \text{J$_{y}$}}$	Table $\,{\large \text{K$_{y}$}}$

  
  

  so we have :

  \begin{equation} {\large \text{J$_{y}$}=\overline{\text{L}}\,\text{B}\,\overline{\text{Y}}+\text{X}\,\overline{\text{Y}}\quad\quad\quad\quad\quad \text{K$_{y}$}=\text{L}\,\overline{\text{X}}\,\text{Y}+\text{L}\,\overline{\text{B}}\,\text{Y}} \end{equation}
  
• 2.5 Simulation on MDLE with 2 JK flip-flops :
  

  Here is the source robot_second.mdl of the module made with 2 JK flip-flops :

  
  
  

  We can load the design with the graphical editor, like this :

  
  
  

  Like with the 2 T flip-flops, we can verify the modeling of the circuit with the MDLE simulator.

3.Implementation on Xilinx Spartan-6 FPGA board - Nexys 3 :

We will initially implement hardware design that we have made above. The software Xilinx ISE can do this by generating a binary file (.bit) which can then be transferred from the PC to the FPGA board. After this first implementation, we will create a GUI to interact in real time with the card.

• 3.1 Design creation with Xilinx ISE software :
  

  ISE allows to synthesize the sequential circuit module of our robot toy. To describe the design, ISE requires a hardware description file written in VHDL (rather used in Europe) or Verilog (rather used in United States). We will choose VHDL because we have a tool to convert a SHDL source into a VHDL source. This tool is called SHDL2VHDL Converter and can be downloaded here : shdl2vhdl2.1.4.jar .

  
  Use now the SHDL source robot_second.mdl (corresponding to the design in paragraph 2.4) and convert it into VHDL with the SHDL2VHDL tool, then we get the file robot_second.vhd :
  
  
  
  library IEEE;
  library UNISIM;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity robot_second is
    port (
      l : in std_logic ;
      b : in std_logic ;
      h : in std_logic ;
      rst : in std_logic ;
      s2 : out std_logic ;
      s1 : out std_logic ;
      s0 : out std_logic
    );
  end robot_second;
  
  architecture synthesis of robot_second is
  
    -- internal signals declarations
    signal jx : std_logic ;
    signal y : std_logic ;
    signal x : std_logic ;
    signal kx : std_logic ;
    signal jy : std_logic ;
    signal ky : std_logic ;
  
  begin
  
    -- concurrent statements
    jx <= (not l) and (not b) and (not y) and (not x) ;
    kx <= (b and x) or (l and x) ;
    jy <= (x and (not y)) or ((not l) and b and (not y)) ;
    ky <= (l and (not b) and y) or (l and (not x) and y) ;
    s2 <= not x ;
    s1 <= (x and (not y)) or ((not x) and y) ;
    s0 <= not x ;
  
    -- sequential statements
    process (h, rst) begin
      if rst = '1' then
        x <= '0' ;
      elsif h'event and h = '1' then
        x <= ((not kx) and x) or (jx and (not x)) ;
      end if ;
    end process ;
    process (h, rst) begin
      if rst = '1' then
        y <= '0' ;
      elsif h'event and h = '1' then
        y <= ((not ky) and y) or (jy and (not y)) ;
      end if ;
    end process ;
  
  end synthesis;
  
  
  

  Into ISE project, we need a file to make the connection between the signals from VHDL design and I/O connectors of the FPGA board. This file is called "User Constraints File" (UCF). We choose the switches SW3, SW2, SW1 and SW0 for respectively entries reset (RST), clock (h), light (l) and noise (b) . For output, we use the LEDs LD2, LD1 and LD0 respectively for outputs s2 (eyes), and (s1, s0) (voice) . So we have the following file robot.ucf :

  # Inputs NET "l"  LOC = "T9"; NET "b"  LOC = "T10"; NET "h"  LOC = "V9"; NET "rst"  LOC = "M8"; # Outputs NET "s0" LOC = "U16"; NET "s1" LOC = "V16"; NET "s2" LOC = "U15";

  We add "robot_second.vhd" and "robot.ucf" in the ISE project, and generate the .bit file. Here is a screenshot :

  
  
  

  For loading under Linux terminal the the "robot_second.bit" generated file, there are 3 commands to do :

  
  
  

  Here is a picture of the board with the inputs (rst, h, l, b) and the initial ouputs (Awake state : 101) :

  
  
  

  In the design, we can add 3 seven-segment displays ; that's we show in this source robotseg.vhd :

  
  
  library IEEE;
  library UNISIM;
  use IEEE.STD_LOGIC_1164.ALL;
  use IEEE.STD_LOGIC_ARITH.ALL;
  use IEEE.STD_LOGIC_UNSIGNED.ALL;
  
  entity robotseg is
    port (
      l : in std_logic ;
      b : in std_logic ;
      h : in std_logic ;
      h1 : in std_logic ;  
      rst : in std_logic ;
      an : inout std_logic_vector (0 to 3) ;
      ss : out std_logic_vector (0 to 2) ;
      ssg : out std_logic_vector (0 to 7)    
    )b;
  end robotseg;
  
  architecture synthesis of robotseg is
  
          -- clock
    
    signal CTR : std_logic_vector (12 downto 0); 
  
    -- buffer signals declarations
    
    signal ss_int : std_logic_vector (0 to 2) ;
  
    -- internal signals declarations
    
    signal jx : std_logic ;
    signal y : std_logic ;
    signal kx : std_logic ;
    signal x : std_logic ;
    signal jy : std_logic ;
    signal ky : std_logic ;
  
  begin
    
   -- concurrent statements
  
    jx <= (not l) and (not b) and (not y) and (not x) ;
    kx <= (b and x) or (l and x) ;
    jy <= (x and (not y)) or ((not l) and b and (not y)) ;
    ky <= (l and (not b) and y) or (l and (not x) and y) ;
    ss_int(2) <= not x ;
    ss_int(1) <= (x and (not y)) or ((not x) and y) ;
    ss_int(0) <= not x ;
    
    -- buffer signals assignations
    
    ss(0 to 2) <= ss_int(0 to 2) ;
    
    process(h) begin
          if h'event and h= '1' then
       if (CTR="0000000000000") then
            if (an(3)='0') then        
          an(3) <= '1';
                      an(0) <= '0';
          ssg <="11111111";
            elsif (an(0)='0') then 
          an(0) <= '1';
          an(1) <= '0';
                    if ss_int(2)='0' then
           ssg <="00000011";
                else ssg <="10011111";
              end if;  
                  elsif (an(1)='0') then                
          an(1) <= '1';
                      an(2) <= '0';
                    if ss_int(1)='0' then
           ssg <="00000011";
                else ssg <="10011111";
        end if;  
                  elsif (an(2)='0') then 
          an(2) <= '1';
                an(3) <= '0';
                    if ss_int(0)='0' then
           ssg <="00000011";
                else ssg <="10011111";
        end if;        
          end if;
       end if;
       CTR<=CTR+"0000000000001";
          if (CTR > "1000000000000") then
              CTR<="0000000000000";
    end if;
          end if;
    end process;
    
    -- sequential statements
    
    process (h1, rst) begin
      if rst = '1' then
        x <= '0' ;
            elsif h1'event and h1 = '1' then
        x <= ((not kx) and x) or (jx and (not x)) ;
      end if ;  
    end process ;
    
          process (h1, rst) begin
      if rst = '1' then
        y <= '0' ;
            elsif h1'event and h1 = '1' then
        y <= ((not ky) and y) or (jy and (not y)) ;
      end if ;
    end process ;
    
  end synthesis;
  
  
  

  The associated user constraints file is robotseg.ucf.

  Here, an example of result with the 3 seven-segment displays; the toy state is Distress (output = 111) :

  
  
  
  
• 3.2 GUI with real time interaction on FPGA board :
  

  We are going to create a graphical user interface interacting in real time with the Nexys 3 board. We will use low-level functions of the dpcutil library in order to send and receive signals from the board. Firstly, we need to integrate into the previous design the USB communication. I/O data are stored in the register at the adress 10 ("regEppAdr=1010" in the dpimref.vhdl). The constraints file is pins.ucf. After building the .bit under ISE and transfering it on the board, we use the following GTK/OpenCV GUI :

  • main.c

  
  
  • 
    

    Compilation script :

  #!/bin/sh INC="/usr/local/include/digilent/adept" LIBDIR="/usr/local/lib64/digilent/adept" CFLAGS="-Wall -I $INC -L $LIBDIR" g++ $CFLAGS -I/usr/include/gtk-2.0/ -I/usr/include/glib-2.0/ -I/usr/lib/glib-2.0/include/ -I/usr/local/include/opencv/ \ -I/usr/include/cairo/ -I/usr/include/pango-1.0/ -I/usr/lib/gtk-2.0/include/ -I/usr/include/atk-1.0/ -L/usr/local/lib/ \ -lcvaux -lhighgui -lcxcore -ldepp -ldmgr main.c

  
  
  This video is showing the good operating of interactions :