library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity robot_second is
	port (
		l : in std_logic ;
		b : in std_logic ;
		h : in std_logic ;
		rst : in std_logic ;
		s2 : out std_logic ;
		s1 : out std_logic ;
		s0 : out std_logic
	);
end robot_second;

architecture synthesis of robot_second is

	-- internal signals declarations
	signal jx : std_logic ;
	signal y : std_logic ;
	signal x : std_logic ;
	signal kx : std_logic ;
	signal jy : std_logic ;
	signal ky : std_logic ;

begin

	-- concurrent statements
	jx <= (not l) and (not b) and (not y) and (not x) ;
	kx <= (b and x) or (l and x) ;
	jy <= (x and (not y)) or ((not l) and b and (not y)) ;
	ky <= (l and (not b) and y) or (l and (not x) and y) ;
	s2 <= not x ;
	s1 <= (x and (not y)) or ((not x) and y) ;
	s0 <= not x ;

	-- sequential statements
	process (h, rst) begin
		if rst = '1' then
			x <= '0' ;
		elsif h'event and h = '1' then
			x <= ((not kx) and x) or (jx and (not x)) ;
		end if ;
	end process ;
	process (h, rst) begin
		if rst = '1' then
			y <= '0' ;
		elsif h'event and h = '1' then
			y <= ((not ky) and y) or (jy and (not y)) ;
		end if ;
	end process ;

end synthesis;