library IEEE; library UNISIM; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity robotseg is port ( l : in std_logic ; b : in std_logic ; h : in std_logic ; h1 : in std_logic ; rst : in std_logic ; an : inout std_logic_vector (0 to 3) ; ss : out std_logic_vector (0 to 2) ; ssg : out std_logic_vector (0 to 7) ); end robotseg; architecture synthesis of robotseg is -- clock signal CTR : std_logic_vector (12 downto 0); -- buffer signals declarations signal ss_int : std_logic_vector (0 to 2) ; -- internal signals declarations signal jx : std_logic ; signal y : std_logic ; signal kx : std_logic ; signal x : std_logic ; signal jy : std_logic ; signal ky : std_logic ; begin -- concurrent statements jx <= (not l) and (not b) and (not y) and (not x) ; kx <= (b and x) or (l and x) ; jy <= (x and (not y)) or ((not l) and b and (not y)) ; ky <= (l and (not b) and y) or (l and (not x) and y) ; ss_int(2) <= not x ; ss_int(1) <= (x and (not y)) or ((not x) and y) ; ss_int(0) <= not x ; -- buffer signals assignations ss(0 to 2) <= ss_int(0 to 2) ; process(h) begin if h'event and h= '1' then if (CTR="0000000000000") then if (an(3)='0') then an(3) <= '1'; an(0) <= '0'; ssg <="11111111"; elsif (an(0)='0') then an(0) <= '1'; an(1) <= '0'; if ss_int(2)='0' then ssg <="00000011"; else ssg <="10011111"; end if; elsif (an(1)='0') then an(1) <= '1'; an(2) <= '0'; if ss_int(1)='0' then ssg <="00000011"; else ssg <="10011111"; end if; elsif (an(2)='0') then an(2) <= '1'; an(3) <= '0'; if ss_int(0)='0' then ssg <="00000011"; else ssg <="10011111"; end if; end if; end if; CTR<=CTR+"0000000000001"; if (CTR > "1000000000000") then CTR<="0000000000000"; end if; end if; end process; -- sequential statements process (h1, rst) begin if rst = '1' then x <= '0' ; elsif h1'event and h1 = '1' then x <= ((not kx) and x) or (jx and (not x)) ; elsif h1'event and h1 = '0' then null; end if ; end process ; process (h1, rst) begin if rst = '1' then y <= '0' ; elsif h1'event and h1 = '1' then y <= ((not ky) and y) or (jy and (not y)) ; elsif h1'event and h1 = '0' then null; end if ; end process ; end synthesis;